ECE517 - VLSI Design Flow


Winter 2020

4 credits


Sneh Saurabh

Teaching Assistants

Jasmine Kaur
Deepayan Banerjee

Info - VLSI Design Flow, IIIT-Delhi


The objective of this course is to develop a basic understanding of the methods, tools and technologies that go into transforming an “idea” into an “integrated circuit”. This course is intended to give an overall perspective of the VLSI design flow, going through various stages of designing such as synthesis, floorplanning, placement, routing etc. and various steps of verification such as simulation, formal methods and timing/power analysis. In this course, ample opportunities will be provided to employ the-state-of-the-art CAD tools and gain a practical understanding of the VLSI design flow. A few representative algorithms that work inside the CAD tools will also be discussed.


At the end of the course the student:
  • Clearly understands each design and verification step in the VLSI design flow, and its purpose/significance
  • Is able to evaluate various trade-offs that need to be made at various steps in the VLSI design flow
  • Is able to design and verify simple VLSI circuits using the state-of-the-art computer aided design (CAD) tools at different levels of abstractions.
  • Understands a few representative algorithms that are used in implementing CAD tools
Course Content (Week-wise schedule):
  1. Introduction: Basic Concepts; Design Styles; Designing vs. Fabrication; Processes involved in taking an "Idea" to RTL: Software/Hardware Partitioning, Behavioral Synthesis
  2. Overview of "RTL to GDS" Design, Verification and Test Flow; Processes after GDS Tapeout to Final Chip;
  3. Design capture: HDL (Verilog), Library and Constraints; 
  4. RTL Simulation and Synthesis; Static Timing Analysis; Power Analysis; 
  5. Introduction to Formal Methods: Equivalence Checking, BDD, SAT;
  6. Logic Synthesis: Optimization, Technology Mapping;  
  7. Design for Test (DFT): Fault Models, Scan Insertion, ATPG, BIST
  8. Overview of CMOS Fabrication Technology; Basics of Physical Design
  9. Floorplanning, Power Planning;
  10. Placement: Techniques and Optimization; 
  11. Clock Tree Synthesis: Distribution, Skew Optimization; Routing: Global and Detailed; ECO
  12. Physical Verification: Extraction, LVS, ERC, DRC; Sign-off
  13. Post-silicon validation, Summing-up and Paper Presentations


  • Assignment and Project-35%
  • Paper Presentation-15%
  • Mid-sem-20%
  • End-sem-30%


  • Digital Circuits
  • Basics of CMOS

Class Timings

Wednesday: 10:30-12:00 and 4:00-5:30 pm.

Office Hours

Instructor: 12:00 pm - 1:00 pm: Wednesday, B-608 (New Academic Building)


There is no prescribed textbook for this course.
At the end of each lecture, appropriate references will be given.